The impact of a particle on a transistor or near a transistor may lead to a parasitic current in an integrated circuit. This impact depends on the ionizing power of the particle, which may be characterized by its linear energy transfer (LET), for example. The quantity of charge generated by a particle corresponds to that implemented during the change of state of a logic node controlled by a transistor. The consequence of this impact may be a change of state or levels of the logic signals, and as a consequence, may lead to errors at the output of the circuit.
To overcome such errors, a known approach is to replicate the signals by replicating the circuits generating such signals. This redundancy allows the probability of obtaining an erroneous signal at the output to be reduced. The probability that all the replicated signals coming from the same signal are all modified at the same time (all the circuits generating these signals are simultaneously subjected to a radiation interference), is much lower than the probability of a non-replicated signal being affected by external radiation. In this way, an analysis of the replicated signals at the output allows the value without interference to be recovered in a more certain manner.
Some sectors of activity, such the aerospace or medical sector, need a component robustness allowing a reliability of response close to 100%. This characteristic is more important than other factors.
One known method of replication allowing such a level of reliability to be obtained at a low physical and financial cost includes triplicating the signals. In other words, three identical electronic components receive the same data signal at the input, and use a majority vote circuit at the output to determine the output signal. These redundant circuits using majority voting are referred to as triple modular redundancy (TMR).
To monitor the state of the electronic components, notably of an integrated circuit, a known technique is to perform a test using an automatic test pattern generator (ATPG) at the output of an integrated circuit production line, and/or, in certain cases, built-in self-tests, during operation of the circuit. Built-in self-tests are referred to as Logic Built-In Self-Test (LBIST).
An ATPG is a test method assisted by a computer used for finding a test sequence at the input which, when it is applied to an integrated circuit, allows test equipment external to the integrated circuit to distinguish between a normal behavior and a defective behavior of the electronic circuit being tested. The test sequences generated are used for testing semiconductor devices at the end of the production line, prior to any use.
A built-in self-test (BIST) method is a mechanism allowing a hardware or software system, or both, to perform its own diagnostic in an autonomous manner. The diagnostic can be triggered automatically, for example, at regular intervals or every time the integrated circuit is powered-up. This may be by triggering a self-monitoring circuit. Otherwise, the diagnostic is in a continuous manner. This mechanism is often found in integrated circuits because it allows the verification of the circuit to be automated.
The test of the LBIST type is a form of a BIST test in which the integrated circuits are configured so as to be capable of carrying out their own operational test, without assistance by a computer or any other external equipment.
The test of the LBIST type offers the advantage of enabling internal electronic circuits to be tested that do not have external connection terminals allowing a direct connection of the circuit to an external automated system, such as an ATPG. It also offers the advantage of being able to trigger a test phase at any given moment in time during the life of the integrated circuit.
The principle of an LBIST test is also based on the generation of at least one test sequence to be injected into the electronic components to be tested, and the analysis of the signal obtained at the output of the components in response to the injected test sequence.
The major drawback is that, when an LBIST test phase is triggered during the operation, the information contained in each of the electronic components is lost. As a consequence, the integrated circuit cannot continue with its operation following the test in exactly the state in which it was prior to the test.